? semiconductor components industries, llc, 2013 may, 2013 ? rev. 3 1 publication order number: nvmfs5826nl/d nvmfs5826nl power mosfet 60 v, 24 m , 26 a, single n ? channel features ? small footprint (5x6 mm) for compact design ? low r ds(on) to minimize conduction losses ? low q g and capacitance to minimize driver losses ? nvmfs5826nlwf ? wettable flanks product ? aec ? q101 qualified and ppap capable ? these are pb ? free devices and rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 60 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r j ? mb (notes 1, 2, 3, 4) steady state t mb = 25 c i d 26 a t mb = 100 c 19 power dissipation r j ? mb (notes 1, 2, 3) t mb = 25 c p d 39 w t mb = 100 c 19 continuous drain cur- rent r ja (notes 1, 3, 4) steady state t a = 25 c i d 8.0 a t a = 100 c 6.0 power dissipation r ja (notes 1 & 3) t a = 25 c p d 3.6 w t a = 100 c 1.8 pulsed drain current t a = 25 c, t p = 10 s i dm 130 a operating junction and storage temperature t j , t stg ? 55 to + 175 c source current (body diode) i s 32 a single pulse drain ? to ? source avalanche energy (t j = 25 c, v dd = 24 v, v gs = 10 v, i l(pk) = 20 a, l = 0.1 mh, r g = 25 ) e as 20 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance maximum ratings parameter symbol value unit junction ? to ? mounting board (top) ? steady state (notes 2, 3) r j ? mb 3.9 c/w junction ? to ? ambient ? steady state (note 3) r ja 42 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. psi ( ) is used as required per jesd51 ? 12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 4. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. marking diagram http://onsemi.com a = assembly location y = year w = work week zz = lot traceability xxxxxx aywzz v (br)dss r ds(on) max i d max 60 v 24 m @ 10 v 26 a 32 m @ 4.5 v g (4) s (1,2,3) n ? channel mosfet d (5,6) s s s g d d d d see detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. ordering information dfn5 (so ? 8fl) case 488aa style 1 1
nvmfs5826nl http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 60 v zero gate voltage drain current i dss v gs = 0 v, v ds = 60 v t j = 25 c 1.0 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 10 a 18 24 m v gs = 4.5 v, i d = 10 a 24 32 forward transconductance g fs v ds = 15 v, i d = 5 a 8.0 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 25 v 850 pf output capacitance c oss 85 reverse transfer capacitance c rss 50 total gate charge q g(tot) v gs = 4.5 v, v ds = 48 v, i d = 10 a 9.1 nc threshold gate charge q g(th) 1.0 gate ? to ? source charge q gs 3.0 gate ? to ? drain charge q gd 4.0 total gate charge q g(tot) v gs = 10 v, v ds = 48 v, i d = 10 a 17 nc switching characteristics (note 6) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 48 v, i d = 10 a, r g = 2.5 9.0 ns rise time t r 32 turn ? off delay time t d(off) 15 fall time t f 24 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 10 a t j = 25 c 0.8 1.2 v t j = 125 c 0.7 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 10 a 15 ns charge time t a 11 discharge time t b 4.0 reverse recovery charge q rr 11 nc 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
nvmfs5826nl http://onsemi.com 3 typical characteristics 012345 figure 1. on ? region characteristics v ds , drain ? to ? source voltage (v) i d , drain current (a) 10 v 4.0 v 4.5 v t j = 25 c v gs = 3.0 v 0 10 20 40 30 0 10 20 40 30 1345 v ds 10 v t j = 25 c t j = ? 55 c t j = 125 c figure 2. transfer characteristics v gs , gate ? to ? source voltage (v) i d , drain current (a) 0.010 0.020 0.030 0.040 246810 figure 3. on ? resistance vs. gate ? to ? source voltage v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) i d = 10 a t j = 25 c 0.010 0.030 510152025 figure 4. on ? resistance vs. drain current and gate voltage i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) v gs = 4.5 v t j = 25 c v gs = 10 v 0.6 0.8 1.0 1.2 1.4 1.6 2.0 ? 50 ? 25 0 25 50 75 100 125 175 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) r ds(on) , drain ? to ? source resistance (normalized) v gs = 10 v i d = 10 a 1000 10000 10 20 30 40 figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (v) i dss , leakage (na) t j = 125 c t j = 150 c v gs = 0 v 0.020 0.040 30 35 45 1.8 100 50 60 3.5 v 0.050 2 40 2.2 2.4 150 50 60
nvmfs5826nl http://onsemi.com 4 typical characteristics 0 200 400 600 800 1000 1200 0 10203040 figure 7. capacitance variation v ds , drain ? to ? source voltage (v) c, capacitance (pf) t j = 25 c v gs = 0 v c iss c oss c rss 0 2 4 6 8 10 02468 12 figure 8. gate ? to ? source voltage vs. total charge q g , total gate charge (nc) v gs , gate ? to ? source voltage (v) v ds = 48 a i d = 10 a t j = 25 c q t q gs q gd 1.0 10 100 1 10 100 figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( ) t, time (ns) v dd = 48 v v gs = 4.5 v i d = 10 a t d(off) t d(on) t f t r 0 10 20 30 50 0.5 0.6 0.7 0.9 figure 10. diode forward voltage vs. current v sd , source ? to ? drain voltage (v) i s , source current (a) v gs = 0 v t j = 25 c 0.1 1 10 1000 0.1 1 10 100 figure 11. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) i d , drain current (a) v gs = 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 1 ms dc 10 ms 40 100 10 14 16 18 1.0 0.8 60 10 s 50 60 figure 12. maximum avalanche energy vs. starting junction temperature t j , starting junction temperature ( c) 175 125 100 75 50 25 0 5 15 20 e as , single pulse drain ? to ? source avalanche energy (mj) 10 i d = 20 a 150
nvmfs5826nl http://onsemi.com 5 typical characteristics 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 13. thermal response pulse time (sec) r ja(t) ( c/w) effective transient thermal resistance 0.1 duty cycle = 0.5 0.2 0.05 0.02 0.01 single pulse device ordering information device marking package shipping ? nvmfs5826nlt1g v5826l dfn5 (pb ? free) 1500 / tape & reel NVMFS5826NLWFT1G 5826lw dfn5 (pb ? free) 1500 / tape & reel nvmfs5826nlt3g v5826l dfn5 (pb ? free) 5000 / tape & reel nvmfs5826nlwft3g 5826lw dfn5 (pb ? free) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nvmfs5826nl http://onsemi.com 6 package dimensions dfn5 5x6, 1.27p (so ? 8fl) case 488aa issue h style 1: pin 1. source 2. source 3. source 4. gate 5. drain *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 0.475 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 3x 4x 4x m 3.00 3.40 0 ??? 3.80 12 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 1.00 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 bsc d1 4.70 4.90 d2 3.80 4.00 e 6.15 bsc e1 5.70 5.90 e2 3.45 3.65 e 1.27 bsc g 0.51 0.61 k 1.20 1.35 l 0.51 0.61 l1 0.05 0.17 a 0.10 c 0.10 c detail a 14 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 3 x c 4 x c seating plane max 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71 0.20 m pin 5 (exposed pad) on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nvmfs5826nl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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